The requirements to the data transmission speed of systems are increasing continuously. In digital systems, the timing of, for example, reading and writing operations between the individual components of a data transmission system and the bus systems connecting these among one another or, generally, transmission paths is increasing in importance for taking over and/or passing on the data correctly. This mutual tuning of the components and/or the interfaces for data transmission is also referred to as calibrating.
In conventional memory systems, for example, a memory controller typically communicates with a plurality of memory components, like for example, DRAM (dynamic random access memory) components. The memory controller and the memory components here are connected to one another via a common bus system such that the memory controller communicates directly with each memory component.
In conventional memory systems, the memory controller calibrates the interface to the individual memory components. The data transfer requirements of the interface, however, only allow a certain number of data lines. This restricts the number of memory components which can be linked to the data bus. Using a buffer chip between the memory controller on the one hand and a plurality of memory components on the other hand may increase the data transmission rate between the memory controller and individual memory components. However, the result is that the memory controller will only calibrate the interface between the memory controller and the buffer chip, whereas the interfaces between the buffer chip and the individual memory components remain uncalibrated since the buffer chip acts in a manner transparent for the memory controller and thus no time slot is provided in the standardized protocol and/or the interface in which the buffer chip may calibrate the interfaces to the memory components.
However, calibration of, if possible, all interfaces is desirable to achieve correct data transmission at high a data transmission rate.